Photonics integration is gaining pace in semiconductors, particularly in heterogeneous multi-die packages, as chipmakers look for innovative solutions to overcome power constraints and deal with growing data volumes.
Since the end of Dennard scaling, which occurred at the 90nm node, power has become increasingly challenging. There are more transistors per mm2, and the wires are thinner, resulting in more resistance, capacitance, and heat generation. Photonics may provide a solution. It could give a step-function improvement, allowing new applications to emerge that are currently restricted by fixed power budgets and copper interconnects.
Optics can aid the transition from an electrical connection interposer to an optical interposer. Once considered an expensive overhead, it is now a faster, lower-power option. New system-level solutions will be possible once the semiconductors and integrated photonics technologies are combined. The cost of power will drop dramatically, and the total cost of the product may decrease.
The reticle limit specifies the largest size a lithography machine can etch. That limit is 33 x 26 — a little over 800mm² for 193nm immersion steppers, which produce a large proportion of today’s chips. Simultaneously, Moore’s Law slows cost-effectiveness for many businesses or design types. It means that the number of transistors that can be economically manufactured on a single silicon has reached its limit.
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