A new project pushes system-in-package designs past the terabit-per-second threshold through extremely sophisticated electronics, CMOS, and optical physics management. The three main system blocks—processor, memory, and interconnects (I/O)—are constantly being reevaluated and are currently the “choke point” in enhancing overall efficiency. Each component strives to improve so as not to receive unfair criticism.
Interconnects must keep up with the advancements in processors and memories as assessed by various metrics, but copper-based links are coming up against some clear obstacles. Electro-optical interconnects, which take an optical physics method, are the solution. Still, getting them to perform as well as they could with silicon has proven extremely difficult.
A recent program presentation revealed some significant advancements. This program’s objectives are neither modest nor humble; they aim to use cutting-edge in-package silicon photonic interfaces to achieve data rates greater than 100 terabits per second (Tb/s) while needing energy of less than one picojoule (pJ)/bit and being capable of kilometer-scale distances.
Even though the Intel/Ayar project didn’t achieve those objectives, it made major progress. Ayar showcased its TeraPHY optical chip technology integrated into a modified commercial IC—an Intel Stratix 10 FPGA—in their virtual demonstration at the Optical Fiber Conference (OFC) 2020 (due to COVID-19), which typically employs copper interconnects.
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